IBIS models for FPGA and the effect on Signal Integrity:
I decided that I need 150 ohm termination on my RX input lines at or near the FPGA 1.5v cmos inputs. I checked to see if an IBIS model is available and found the above link and after accepting terms, down loaded cyclone2.zip
The new circuit is the same except that the IBIS generic input is added. Image included at the bottom of this post. It appears that the IBIS model does not include a pull down resister. I was a bit surprised until I read the document:
The 1.5v LVCMOS IOs do not have internally sellectable input termination. I have re-run the transient simulation stepping R1 (termination resistor) from 50 to 300 ohms. Below are the results. As before, far-end ringing signal simulation are shown in red and near-end ringing waveforms are shown in green.
The addition of the IBIS model input does move the location and period of the ringing. I am glad that I decided to include it. So it really does look like termination resistors are important to the layout .
Below is the circuit as shown before but with the added IBIS generic input model at the far right.
(Added Note 8/11/2018: I added the Ideal parameters to the TL then I noticed I could change length to anything an get the same results ..... Definitely a sign that there are problems with the model. More about this in my next post on Transmission Line modelling lossy vs Ideal.)