Monday, August 6, 2018

Signal Integrity and IBIS models:

While creating the layout for the PCIe card I have needed to evaluate signal integrity on  all of the RX/TX connections.

IBIS models for the TI XIO1100 are available at:

IBIS stands for IO Buffer Information Specification and it is a way for the IP provider to hide details of the design while providing enough information about the design to enable Signal Integrity simulation to create quality signal connection to the IO pins either input or output that will be analyzed via spice simulation so as to  properly terminate the pins and eliminate impedance miss-match  that can cause signal reflections and cross-talk that will degrade the signal path to and from the pins.

To use the TI  IBIS model I have needed to download a simulator tool.   I have chosen Micro-Cap v12

Micro-Cap has a generic IBIS model that can be added to the circuit.  Once it is added you simply read in the IBIS model and it is ready to go.  Surprisingly easy for a first-time MICRO - CAP user.  Then you model the signal path using a transmission line model.  I have used an ideal model for the transmission line and set the characteristic impedance and TD per the impedance calculator described at the end of this post.  In addition, I have added the generic IBIS model driver and enabled it in my circuit.  I have also placed a voltage source at the driver input and given it a  3.3v pulse train with a TR/TF (time rise/fall) of  0.1ns and a period on 8ns. This would be similar timing to the  XIO1100 125 MHz clock.  R1 in this case would be a terminating resistor at the FPGA input.  This first setup does not include an IBIS model at the FPGA input but I believe an IBIS input would be fairly easy to arrange.  Just use the Micro-CAP generic IBIS input receiver and once again load the model.

Here below I have stepped R1 from 100 ohms to 10k ohms and performed transient analysis. The reflections on far-end (red) and near-end (green) get worse as the terminating resistance gets higher. At 10k ohms the reflections at the far-end get as high as 2.3 volts.  Near-end transients are those at the input end of the transmission line and far-end transients are at the load or terminating resistor (R1).  I still need to check what the FPGA input impedance is however it is likely higher then that of the terminating resistor, R1.

The real circuit with similar reflection where R1 = 10k would have problems with high voltage spikes on FPGA inputs  and cross-talk on neighboring nets.  However a terminating resistor near Zo = 139 ohms would cause the reflections to go away.  What I have been happy to see here is that the circuit does not appear to need near-end termination.  I expect that I will need about 139 ohm termination to GND at the far end. (maybe 150 ohms) .

The FR4 PCB paths can be seen as a transmission line that have an impedance which needs to be matched on both ends if the the length is longer than about 1/6th the wavelength of the signal being transmitted. Therefore for a single ended microstrip that is 5 mils in width and a 2-stack build up, there is a characteristic impedance, Zo of about 139 ohms.  If you were thinking that this should have been more like 50 ohms you would be right for a 4-layer board.  You can try this yourself.  There are several tools on the internet for calculating characteristic impedance based on line widths , thicknesses and distance between plates. i.e core thickness.  If this were a 4 layer build-up the distance between layer would have been 0.23 mm  of about 9 mils  (FR4).   Which would have been a larger capacitance a lower impedance.  I cannot quote a reasonable number since the dielectric constant would be different.

Since I am intending to have my boards manufactured very cheaply through PCBWAY. I have asked them what the relative dielectric is.  They have quoted 5.4 which I have entered into the below impedance calculator.,

Comments are welcome below.


impedance checker:
Spectrum Software:
XIO1100 IBIS model:

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