Monday, August 20, 2018

Board Design nearing completion  added VGA:

I removed the unnecessary termination resistors since my simulations showed they were not needed. For more information about that please see my previous posts. I also fixed the GND-VSS problem. Seems I had both however they were unconnected.

For Diagnostic purposes I added the VGA D-sub connector and D to A ladder resistors for red(2:0) green(2:0) and blue(1:0) digital signals.  H_sync and V_sync are connected directly from outputs on the FPGA. I will need one of the two PLLs on the FPGA configured to 108 MHz for the VGA signaling. Its good that this FPGA has two PLLs.

  I have a stand alone FPGA card that I will use to test the VGA capability before having this first pass experimental board created.  If I don't have VGA working there is no way to tell what is going on inside the system and so a board without VGA capabilities is completely useless.



As can be seen above I have labeled the board v1.00x where x indicates that this is an experimental board for the purpose of  researching the interface and debugging. The VGA interface will be very simple.  nothing fancy; only for showing incoming RX signals from the PHY so as to respond to enumeration and training messages.  The board is supposed to be 4-layer but I have chosen to work with a 2-layer board initially for cost reasons.   I will continue to do so on these experimental board versions as long as it can not be of any more use experimentally.  It is possible that I will find out that the 2-layer board is of no use the very first pass.  However it is so cheap to build a 2-layer board that it is worth the risk. 

A Note to self:  I must also add noise decoupling capacitance on 3.3v and 1.5v voltage regulator input pins.  Just so I don't forget.


Comments are welcome and appreciated.

Will

www.c1960.net




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