Monday, August 20, 2018

Board Design nearing completion  added VGA:

I removed the unnecessary termination resistors since my simulations showed they were not needed. For more information about that please see my previous posts. I also fixed the GND-VSS problem. Seems I had both however they were unconnected.

For Diagnostic purposes I added the VGA D-sub connector and D to A ladder resistors for red(2:0) green(2:0) and blue(1:0) digital signals.  H_sync and V_sync are connected directly from outputs on the FPGA. I will need one of the two PLLs on the FPGA configured to 108 MHz for the VGA signaling. Its good that this FPGA has two PLLs.

  I have a stand alone FPGA card that I will use to test the VGA capability before having this first pass experimental board created.  If I don't have VGA working there is no way to tell what is going on inside the system and so a board without VGA capabilities is completely useless.



As can be seen above I have labeled the board v1.00x where x indicates that this is an experimental board for the purpose of  researching the interface and debugging. The VGA interface will be very simple.  nothing fancy; only for showing incoming RX signals from the PHY so as to respond to enumeration and training messages.  The board is supposed to be 4-layer but I have chosen to work with a 2-layer board initially for cost reasons.   I will continue to do so on these experimental board versions as long as it can not be of any more use experimentally.  It is possible that I will find out that the 2-layer board is of no use the very first pass.  However it is so cheap to build a 2-layer board that it is worth the risk. 

A Note to self:  I must also add noise decoupling capacitance on 3.3v and 1.5v voltage regulator input pins.  Just so I don't forget.


Comments are welcome and appreciated.

Will

www.c1960.net




Saturday, August 11, 2018

Transmission Line modeling:  Micro-Cap v12:

So now when I set model type  to lossy I see different simulation results:

Parameters: R=96.7ohms/in  C=1.09pF/in  L=21.217nH/in Len=29.5mm/25.4(mm/in)  = 1.16 in.

It appears that model type ideal does not include parameter  Len.  However since my length of 29.5mm is close to an inch (1.16 inch) I was getting results that seemed reasonable.  However the addition of loss or line resistance I have a dampening and attenuation affect.

Again I have stepped R1 (termination resistor) from 50 ohms to 300 ohms.


If I set model type to Ideal  and change parameters as follows:

Zo = 139 ohms   Td = 152 ps/in * 1.16 in = 176.32ps 



So as you can see from the two plots, the difference is the dampening /attenuation of the signal at the far-end and less noticeably at the near-end.  Far-end is red and near-end is green.  What is similar in both simulations (lossy vs. ideal) is the timing; they seem roughly the same.

And .... lossy model w/ no termination:

I have just added a line indicating the timing at 1.5v * 90%  =  1.35v.  Since it is unclear to me where a clock edge would be located this is just for reference.   More on this when I consider timing.  For now I think I will remove termination resistors.







Comments are welcome:







Thursday, August 9, 2018

IBIS models for FPGA and the effect on Signal Integrity:

Refference:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/ibis/ibs-ibis_index.html?language=en_US

I decided that I need 150 ohm termination on my RX input lines at or near the FPGA 1.5v cmos inputs.   I checked to see if an IBIS model is available and found the above link and after accepting terms, down loaded cyclone2.zip

The new circuit is the same except that the IBIS generic input is added.  Image included at the bottom of this post.  It appears that the IBIS model does not include a pull down resister.  I was a bit surprised until I read the document:


The 1.5v LVCMOS IOs do not have internally sellectable input termination.   I have re-run the transient simulation stepping R1 (termination resistor) from 50 to 300 ohms.  Below are the results. As before, far-end ringing signal simulation are shown in red and near-end ringing waveforms are shown in green.




The addition of the IBIS model input does move the location and period of the ringing. I am glad that I decided to include it.  So it really does look like termination resistors are important to the layout .

Below is the circuit as shown before but with the added IBIS generic input model at the far right.

(Added Note 8/11/2018:  I added the Ideal parameters to the TL then I noticed I could change length to anything an get the same results ..... Definitely a sign that there are problems with the model. More about this in my next post on Transmission Line modelling lossy vs Ideal.)


Consequently I am adding termination resistors to the layout.  I have found some appropriate Panasonic surface mount resisters in a 1206 package and  I am currently adding them to the bottom side of the circuit board so as to be close to RX inputs.   This includes a via between resistor and input pin and it may be worth modelling that via in the future.  Possibly more on this later.




As always comments/suggestion  are welcome:



Monday, August 6, 2018

Signal Integrity and IBIS models:


While creating the layout for the PCIe card I have needed to evaluate signal integrity on  all of the RX/TX connections.


IBIS models for the TI XIO1100 are available at:  http://www.ti.com/product/XIO1100/toolssoftware

IBIS stands for IO Buffer Information Specification and it is a way for the IP provider to hide details of the design while providing enough information about the design to enable Signal Integrity simulation to create quality signal connection to the IO pins either input or output that will be analyzed via spice simulation so as to  properly terminate the pins and eliminate impedance miss-match  that can cause signal reflections and cross-talk that will degrade the signal path to and from the pins.

To use the TI  IBIS model I have needed to download a simulator tool.   I have chosen Micro-Cap v12


Micro-Cap has a generic IBIS model that can be added to the circuit.  Once it is added you simply read in the IBIS model and it is ready to go.  Surprisingly easy for a first-time MICRO - CAP user.  Then you model the signal path using a transmission line model.  I have used an ideal model for the transmission line and set the characteristic impedance and TD per the impedance calculator described at the end of this post.  In addition, I have added the generic IBIS model driver and enabled it in my circuit.  I have also placed a voltage source at the driver input and given it a  3.3v pulse train with a TR/TF (time rise/fall) of  0.1ns and a period on 8ns. This would be similar timing to the  XIO1100 125 MHz clock.  R1 in this case would be a terminating resistor at the FPGA input.  This first setup does not include an IBIS model at the FPGA input but I believe an IBIS input would be fairly easy to arrange.  Just use the Micro-CAP generic IBIS input receiver and once again load the model.



Here below I have stepped R1 from 100 ohms to 10k ohms and performed transient analysis. The reflections on far-end (red) and near-end (green) get worse as the terminating resistance gets higher. At 10k ohms the reflections at the far-end get as high as 2.3 volts.  Near-end transients are those at the input end of the transmission line and far-end transients are at the load or terminating resistor (R1).  I still need to check what the FPGA input impedance is however it is likely higher then that of the terminating resistor, R1.

The real circuit with similar reflection where R1 = 10k would have problems with high voltage spikes on FPGA inputs  and cross-talk on neighboring nets.  However a terminating resistor near Zo = 139 ohms would cause the reflections to go away.  What I have been happy to see here is that the circuit does not appear to need near-end termination.  I expect that I will need about 139 ohm termination to GND at the far end. (maybe 150 ohms) .










The FR4 PCB paths can be seen as a transmission line that have an impedance which needs to be matched on both ends if the the length is longer than about 1/6th the wavelength of the signal being transmitted. Therefore for a single ended microstrip that is 5 mils in width and a 2-stack build up, there is a characteristic impedance, Zo of about 139 ohms.  If you were thinking that this should have been more like 50 ohms you would be right for a 4-layer board.  You can try this yourself.  There are several tools on the internet for calculating characteristic impedance based on line widths , thicknesses and distance between plates. i.e core thickness.  If this were a 4 layer build-up the distance between layer would have been 0.23 mm  of about 9 mils  (FR4).   Which would have been a larger capacitance a lower impedance.  I cannot quote a reasonable number since the dielectric constant would be different.

Since I am intending to have my boards manufactured very cheaply through PCBWAY. I have asked them what the relative dielectric is.  They have quoted 5.4 which I have entered into the below impedance calculator.,



Comments are welcome below.

References:

impedance checker:          http://www.mantaro.com/resources/impedance-calculator.htm
Spectrum Software:          http://www.spectrum-soft.com/index.shtm
XIO1100 IBIS model:       http://www.ti.com/product/XIO1100/toolssoftware