Monday, July 23, 2018

Current Project ...........

PCEe 1x  gen1 link @ 2.5GHz   (For the Hobbyist)

Eagle Cad v9.1.0

When I was much younger  I created my first PCI design.  I created it from a scrap CGA PCI card. This was a full length card as shown below.

I cut all of the TTL pins off the CGA card by slicing the pins with an exacto knife with the exception of the the power/GND pins  usually the bottom left and upper right pin E.G pin 7 and 14 of a 14 pin dip.

Then I desoldered all of the TTL chips (only pwr/gnd pins left to desolder) and carefully bent each sliced pin so that they were now sticking out of the plastic DIP and horizontal for a nice surface to solder to.  I would create my own IO Address by re-inserting the decoder chips to decode address bits on the PCI interface card. I would enable my circuits (usually something like an ADC) based on that decoded address and  PCI READ/WRITE signals.

I would place the TTL chips back in the card and make point-to-point connections between them by soldering wire-wrap wires to now horizontal and disconnected pins.  The only circuitry used in the original card would be of course the PCI pins and the power/gnd connections to TTL components.

I would then write assembly code in DOS/(Windows Command)  debug.exe  to access my card and communicate with it.

Not so easy to find this old project board but at least here is a CGA card with lots of  Digital TTL components. These old cards had a nice easy parallel interface. It was easy to use a DOS IO read/write to access them. One just needed to use the same IO address that the card decodes. Also that IO address can not match any other IO mapped device connected to the PC.


Today PCIe cards have fewer pins but much faster communication and very complex interface. This pictured card has 1 lane of  serial communications. There can be as many as 16 lanes and at gen1 speed (slowest speed currently)  it can transfer 250M-bytes per lane -per second. 

Ahhh if it were only as easy as that these days.  Now the PCIe communications are serial communications that start at 2.5 Gbps...   They Send 10bits via 8b/10b encoding plus pseudo random scrambling ... It is really very complicated now........  plus there is a lot of channel setup and training and host/endpoint enumeration and speed negotiation that must happen first before any communication can start.

Believe me it is so complicated now.. its a nightmare for the hobbyist !

Therefore  I am attempting to bridge that difficult interface.  There are other PCI cards currently available but they are very expensive.  Not priced for the hobbyist. If I can produce a PCIe card with 1x lane then the whole difficult communication with the PC can be made simple again.  And the hobbyist can get access to a max 250 M-bytes-per-second data for his project.  I am using the TI XI01100 chip for the PHY chip and reading/writing to it in 16 bit words at a time at 125 MHZ with a Cyclone II FPGA.  The coding will be difficult. ...  Coding here should be understood as hardware configuring since this is a FPGA. I am not writing code for a MCU to perform rather configuring hardware in the FPGA.   FPGAs can be much faster than a MCU because they do not run serially. The hardware configured all runs in parallel at the internal clock which is in this case 125 MHz

I have performed a basic layout of the circuit.....picture added at the top and below.

The TX data (0:15) and RX data (0:15)  pins can be seen lower left corner and lower right corner of the Cyclone FPGA respectively which is a 144 pin QFP package. (pictured above) I needed to route the pins from the TI PHY  (CBGA device below the FPGA) that are closest to the FPGA to pins to that are the furthest on the FPGA.  The pins that are furthest from the FPGA need to route to the nearest pins. for both the TX and RX data pins (16 bit buses each)

This was done to try to keep the wire lengths equal so that the electrical data arrival times can be somewhat equal.  At 125 MHz there is   1  /  125 MHz  =  8 ns of time to get those electrical signals propagating  29.5  mm  to meet a setup time with the clock signal that should happen at the beginning of the next  8ns clock period.  Not sure what the setup time is. Maybe ~  1ns?  ... More on this later.

In Eagle you can get wire lengths by typing   run  length_freq_ri   at the command prompt.
above lengths are in mm.

More to come as I continually update this blog .......

Comments are welcome below:

Tell me what you think.  I am trying for a low-cost card.  Starting with just a two-sided board for now except at the PCIe pins themselves that plug into the PCIe connector will be doubled up.  I am sure it will take several board attempt and configuring cycles on the FPGA to get something working.  I don't want to spend a lot of money at each board refresh cycle.


TI XIO1100:

1 comment:

  1. I started looking into ways to get a PCIe interface onto cheaper FPGAs, and found (only) your blog post as reference designs. Impressive work :) Did you ever publish the schematics, or would you consider doing so?
    I'm leaning towards a Lattice iCE40 or ECP5 FPGA (which are supported with open-source tools), and possibly a mini-PCIe layout.