Thursday, July 26, 2018

FPGA configuration.:  Quartus.

Note:  Verilog/VHDL coding is not for beginners.  Where I say the word easy here, I do not mean easy for the beginner.  Skip to the end of this document (Who can do this) for a better understanding of the skills needed  ....

I have been using Quartus which is  a very nice software package available to configure Alterra FPGAs, It has an easy-to-use verilog/vhdl interface.  If you are familiar with verilog/vhdl.  It also has everything you need to configure powerful FPGA devices that give relatively high performance. I was very impressed with the very low cost of some of these FPGA devices in DIGI-KEY

For example, a  low-end Cyclone II device can be in a  144 pin LQFP package that is capable of internal clock speeds greater than a hundred MHz and has two internal PLLs.  The software  includes wizard macro creation of many blocks such as FIFOs and multipliers and a lot more. The parts can cost as low as about 11 dollars US.  The higher quality FPGAs of course are much more expensive and capable of a lot more.  Some of the software generated IP needs to be licensed as well.

Pictured here is the windows 32bit version for windows 7.   It is simple to get started. Just download the Quartus software from Alterra. (soon to be Here I have downloaded and am running v12.0

The flow is as follows:

1:    write some verilog/vhdl  code:  I prefer verilog.
Use the macro creator for common block such as memory blocks etc. Include them in your top level design. Below I have used the wizard and created a PLL and FIFO and included them in the top-level verilog.  The Hierarchy editor lets you see all of the sub blocks in your design and the Files tab has a list of all of the verilog modules.  Each of them can be viewed in the design code viewer.

2:     compile it.  (purple triangle Icon)

The compile button starts the compile process and produces errors and warnings. If you have only warnings left, you have successfully compiled.  The compiler does some other important things such as Synthesis and design Elaboration and layout.  You can even pull open a RTL viewer that lets you look at the gate level netlist after you have a successful synthesis.   There is a state machine viewer (not shown here) as well that lets you pull open a graphics representation of your state machine. My state machine is in lower hierarchical level. The RTL viewer lets you navigate these hierarchies as well.

Once you have a compiled and synthesized design. You are able to go into the pin editor/planner.

3: Run Pin Assignment tools

The pin planner tool lets you assign on the FPGA layout where your IOs will go.  And lets you select the type and drive strength of IOs.  This becomes very important as you move from a design to a design layout phase because you will need to carefully plan those locations in such a way to allow the signals to propagate in a reasonable manor to/from other devices in your design.

As you can partially see I have in this example a tx_data[0:15]  and an rx_data[0:15] sets of pins. These will be routing off the FPGA to pins on the PHY chip.  I have needed to group them in different corners of the FPGA,  The RX pins are in the lower right corner of the FPGA and the TX are in the lower left corner.  I have changed the bus data bit order some as I have been working through the part layout on circuit board.  The PHY is the TI XIO1100 part and it has 100 CBGA balls that have a layout of 25 pins per side, (two rows of 9 balls and a more inwardly located and centered row of 7 balls)  In some case it makes sense on the FPGA to change pin order to accommodate routing from CBGA to LQFP pins on the Cyclone II.  You are free to change whatever bus bit you like wherever you like on the FPGA.  The word 'free' here should mean relatively speaking free.

4: Program the Device:

When you are all done of course you can program the FPGA using a USB Blaster  available on ebay for around 6 dollars US. A driver for the USB blaster needs to be installed on the computer.

 You just need to tell the software what your programming device is and what device you have connected to it.

Who can do this:

For a beginner this is complicated and probably not for you.  You should know how to code and debug verilog/vhdl.  You should understand the type of coding structures that synthesize well into an ASIC/FPGA design.  If you feel strongly that you can accomplish anything you set your mind to ... then go for it.   Reach for the moon.  JFK would do it!   If you have software questions there are a number of sources available to you including YouTube channels.  Search youtube for Quartus tutorial.  They will not help you with your verilog I am sure but they can certainly help you through Quartus software issues.

If you are an electronics student and will be working with verilog/vhdl as part of your studies than go ahead and get your feet wet now! If you are studying for a BSEE degree just jump in!

For someone that has experience in ASIC development it is refreshingly simple.

In the ASICs environment design cycles can take months to complete. Sometimes half a year. This FPGA design cycle is much simpler.  It is amazing the performance that is available !

Comments are welcome below:

Monday, July 23, 2018

Current Project ...........

PCEe 1x  gen1 link @ 2.5GHz   (For the Hobbyist)

Eagle Cad v9.1.0

When I was much younger  I created my first PCI design.  I created it from a scrap CGA PCI card. This was a full length card as shown below.

I cut all of the TTL pins off the CGA card by slicing the pins with an exacto knife with the exception of the the power/GND pins  usually the bottom left and upper right pin E.G pin 7 and 14 of a 14 pin dip.

Then I desoldered all of the TTL chips (only pwr/gnd pins left to desolder) and carefully bent each sliced pin so that they were now sticking out of the plastic DIP and horizontal for a nice surface to solder to.  I would create my own IO Address by re-inserting the decoder chips to decode address bits on the PCI interface card. I would enable my circuits (usually something like an ADC) based on that decoded address and  PCI READ/WRITE signals.

I would place the TTL chips back in the card and make point-to-point connections between them by soldering wire-wrap wires to now horizontal and disconnected pins.  The only circuitry used in the original card would be of course the PCI pins and the power/gnd connections to TTL components.

I would then write assembly code in DOS/(Windows Command)  debug.exe  to access my card and communicate with it.

Not so easy to find this old project board but at least here is a CGA card with lots of  Digital TTL components. These old cards had a nice easy parallel interface. It was easy to use a DOS IO read/write to access them. One just needed to use the same IO address that the card decodes. Also that IO address can not match any other IO mapped device connected to the PC.


Today PCIe cards have fewer pins but much faster communication and very complex interface. This pictured card has 1 lane of  serial communications. There can be as many as 16 lanes and at gen1 speed (slowest speed currently)  it can transfer 250M-bytes per lane -per second. 

Ahhh if it were only as easy as that these days.  Now the PCIe communications are serial communications that start at 2.5 Gbps...   They Send 10bits via 8b/10b encoding plus pseudo random scrambling ... It is really very complicated now........  plus there is a lot of channel setup and training and host/endpoint enumeration and speed negotiation that must happen first before any communication can start.

Believe me it is so complicated now.. its a nightmare for the hobbyist !

Therefore  I am attempting to bridge that difficult interface.  There are other PCI cards currently available but they are very expensive.  Not priced for the hobbyist. If I can produce a PCIe card with 1x lane then the whole difficult communication with the PC can be made simple again.  And the hobbyist can get access to a max 250 M-bytes-per-second data for his project.  I am using the TI XI01100 chip for the PHY chip and reading/writing to it in 16 bit words at a time at 125 MHZ with a Cyclone II FPGA.  The coding will be difficult. ...  Coding here should be understood as hardware configuring since this is a FPGA. I am not writing code for a MCU to perform rather configuring hardware in the FPGA.   FPGAs can be much faster than a MCU because they do not run serially. The hardware configured all runs in parallel at the internal clock which is in this case 125 MHz

I have performed a basic layout of the circuit.....picture added at the top and below.

The TX data (0:15) and RX data (0:15)  pins can be seen lower left corner and lower right corner of the Cyclone FPGA respectively which is a 144 pin QFP package. (pictured above) I needed to route the pins from the TI PHY  (CBGA device below the FPGA) that are closest to the FPGA to pins to that are the furthest on the FPGA.  The pins that are furthest from the FPGA need to route to the nearest pins. for both the TX and RX data pins (16 bit buses each)

This was done to try to keep the wire lengths equal so that the electrical data arrival times can be somewhat equal.  At 125 MHz there is   1  /  125 MHz  =  8 ns of time to get those electrical signals propagating  29.5  mm  to meet a setup time with the clock signal that should happen at the beginning of the next  8ns clock period.  Not sure what the setup time is. Maybe ~  1ns?  ... More on this later.

In Eagle you can get wire lengths by typing   run  length_freq_ri   at the command prompt.
above lengths are in mm.

More to come as I continually update this blog .......

Comments are welcome below:

Tell me what you think.  I am trying for a low-cost card.  Starting with just a two-sided board for now except at the PCIe pins themselves that plug into the PCIe connector will be doubled up.  I am sure it will take several board attempt and configuring cycles on the FPGA to get something working.  I don't want to spend a lot of money at each board refresh cycle.


TI XIO1100: