FPGA configuration.: Quartus.
Note: Verilog/VHDL coding is not for beginners. Where I say the word easy here, I do not mean easy for the beginner. Skip to the end of this document (Who can do this) for a better understanding of the skills needed ....
I have been using Quartus which is a very nice software package available to configure Alterra FPGAs, It has an easy-to-use verilog/vhdl interface. If you are familiar with verilog/vhdl. It also has everything you need to configure powerful FPGA devices that give relatively high performance. I was very impressed with the very low cost of some of these FPGA devices in DIGI-KEY
For example, a low-end Cyclone II device can be in a 144 pin LQFP package that is capable of internal clock speeds greater than a hundred MHz and has two internal PLLs. The software includes wizard macro creation of many blocks such as FIFOs and multipliers and a lot more. The parts can cost as low as about 11 dollars US. The higher quality FPGAs of course are much more expensive and capable of a lot more. Some of the software generated IP needs to be licensed as well.
Pictured here is the windows 32bit version for windows 7. It is simple to get started. Just download the Quartus software from Alterra. (soon to be Intel.com) Here I have downloaded and am running v12.0
The flow is as follows:
1: write some verilog/vhdl code: I prefer verilog.
Use the macro creator for common block such as memory blocks etc. Include them in your top level design. Below I have used the wizard and created a PLL and FIFO and included them in the top-level verilog. The Hierarchy editor lets you see all of the sub blocks in your design and the Files tab has a list of all of the verilog modules. Each of them can be viewed in the design code viewer.
2: compile it. (purple triangle Icon)
The compile button starts the compile process and produces errors and warnings. If you have only warnings left, you have successfully compiled. The compiler does some other important things such as Synthesis and design Elaboration and layout. You can even pull open a RTL viewer that lets you look at the gate level netlist after you have a successful synthesis. There is a state machine viewer (not shown here) as well that lets you pull open a graphics representation of your state machine. My state machine is in lower hierarchical level. The RTL viewer lets you navigate these hierarchies as well.
Once you have a compiled and synthesized design. You are able to go into the pin editor/planner.
3: Run Pin Assignment tools
The pin planner tool lets you assign on the FPGA layout where your IOs will go. And lets you select the type and drive strength of IOs. This becomes very important as you move from a design to a design layout phase because you will need to carefully plan those locations in such a way to allow the signals to propagate in a reasonable manor to/from other devices in your design.
As you can partially see I have in this example a tx_data[0:15] and an rx_data[0:15] sets of pins. These will be routing off the FPGA to pins on the PHY chip. I have needed to group them in different corners of the FPGA, The RX pins are in the lower right corner of the FPGA and the TX are in the lower left corner. I have changed the bus data bit order some as I have been working through the part layout on circuit board. The PHY is the TI XIO1100 part and it has 100 CBGA balls that have a layout of 25 pins per side, (two rows of 9 balls and a more inwardly located and centered row of 7 balls) In some case it makes sense on the FPGA to change pin order to accommodate routing from CBGA to LQFP pins on the Cyclone II. You are free to change whatever bus bit you like wherever you like on the FPGA. The word 'free' here should mean relatively speaking free.
4: Program the Device:
When you are all done of course you can program the FPGA using a USB Blaster available on ebay for around 6 dollars US. A driver for the USB blaster needs to be installed on the computer.
You just need to tell the software what your programming device is and what device you have connected to it.
Who can do this:For a beginner this is complicated and probably not for you. You should know how to code and debug verilog/vhdl. You should understand the type of coding structures that synthesize well into an ASIC/FPGA design. If you feel strongly that you can accomplish anything you set your mind to ... then go for it. Reach for the moon. JFK would do it! If you have software questions there are a number of sources available to you including YouTube channels. Search youtube for Quartus tutorial. They will not help you with your verilog I am sure but they can certainly help you through Quartus software issues.
If you are an electronics student and will be working with verilog/vhdl as part of your studies than go ahead and get your feet wet now! If you are studying for a BSEE degree just jump in!
For someone that has experience in ASIC development it is refreshingly simple.
In the ASICs environment design cycles can take months to complete. Sometimes half a year. This FPGA design cycle is much simpler. It is amazing the performance that is available !